LT24102 Specifications

Auto-Configuration - Five Way 16/8 lane PCIe Gen 2.0 SoC

FEATURES

PCI Express Interfaces

• PCI Express 2.0 compliant. Backward compatible with PCI Express 1.2a

• 48 lanes of 5 Gbps SERDES

• One x16 upstream port

• Two x16 or one x16 and two x8 or four x8 downstream port (Auto configuration)

• Lane reversal on all ports

• Supports PCI Power Management Interface specification

• Unused SERDES are disabled to save power

• Supports Advanced Configuration and Power Interface Specification,Revision 2.0 (ACPI) supporting active link state

  
  

PCI Express Switch Port

• Up to five PCI Express switch ports

• Fully Compliant with PCI Express logical protocol layers, Data Link Layer and Transaction Layer

• One virtual channel

• Eight Traffic Classes

• Maximum payload size of 256B

• Legacy PCI INTx emulation

• MSI Support

• Support for PCI Express Advanced Error Logging

Embedded RISC

• Tensilica Diamond Architecture 32-bit RISC

• 300 Mhz clock

• 64 Kbytes on-chip instruction memory

• 32 KBytes on-chip data memory

• On chip DMA engine to enable PCIe packet generation and reception

• Real time control over the switch operation

Other

• 483 FCBGA 23 x 23 mm package with 1 mm pitch

• Two LED outputs per PCIe interface

• Jtag Interface with AC and DC JTAG Support

• Optional four wire EEPROM interface

• Optional I²C bus

• Single 100 Mhz reference clock

• Power consumption: 6 Watts